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Fm Page 42 Wednesday, October 8, 2003 10:58 AM P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 Low Power – Is your end product battery- or solar-powered? Does your design require the lowest power devices possible? Do you have heat dissipation concerns? System-Level Functions – Does your board have multi-voltage devices? Do you need to level shift between these devices? Do you need to square up clock edges? Do you need to interface to memories and microprocessors? XC9500 ISP CPLD OVERVIEW The high-performance, low-cost XC9500 families of Xilinx CPLDs are targeted for leading-edge systems that require rapid design development, longer system life, and robust field upgrade capability.
The VFM increases logic optimization by implementing any two input logic functions before entering the macrocell. fm Page 50 Wednesday, October 8, 2003 10:58 AM P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 FIGURE 2-24: COOLRUNNER XPLA3 LOGIC BLOCK Each macrocell supports combinatorial or registered inputs, preset and reset, configurable D, T, or latch functions. If a macrocell needs more product terms, it simply gets the additional product terms from the PLA array. FoldBack NANDs XPLA3 utilizes FoldBack NANDs to increase the effective product term width of a programmable logic device.
Each Spartan-IIE CLB contains four logic cells, organized in two similar slices. In addition to the four basic logic cells, the Spartan-IIE CLB contains logic that combines function generators to provide functions of five or six inputs. 5 logic cells. fm Page 36 Wednesday, October 8, 2003 10:58 AM P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 FIGURE 2-12: SPARTAN-IIE LOGIC CELL Spartan-IIE function generators are implemented as 4-input LUTs. In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM.